1. Field
Example embodiments relate to a semiconductor integrated circuit, and for example, to a single ended pseudo differential interconnection circuit and/or a single ended pseudo differential signaling method.
2. Description of Related Art
Impedance matching may be important for reducing reflection and/or ringing on a high-speed signal transmission line. Transmission lines including signals having a limited slew rate, a resistor termination, and/or a diffused resistor termination may be used for impedance matching. Transmission lines having a non-resonant length and/or impedance control drivers may be used for impedance matching.
Many CMOS integrated circuits may be interconnected to transmit voltage signals from one part to another part. A transmitting part may be a CMOS inverter and/or a receiving part may be a simple CMOS amplifier, a differential amplifier, or a comparator. The CMOS receiving part may act as a high impedance termination or a load on a transmission line. A high impedance termination may be problematical because a switching response time or signal delay may be determined by the transmitting part's capability of charging a transmission line capacitor and/or a load capacitor. Capacitive coupling and/or large voltage switching on neighboring signal lines may generate a large noise voltage on signal transmission lines.
Accordingly, two conventional interconnection methods that may not be affected by a voltage signal are used. The first conventional method is single sided/single ended interconnection and the second conventional method is differential interconnection. The conventional differential interconnection may be preferable for reduction of common mode noise. However, the conventional differential interconnection may require two transmission lines and/or need as many as twice as many input/output pads and packaging pins as the number of input/output pads and packaging pins of the conventional single sided/single ended interconnection in I/O application. The necessity for two transmission lines may complicate a chip surface area in a specific CMOS application.
Single sided/single ended pseudo differential interconnection may have several advantages including removal of power supply voltage noise. A pseudo differential amplifier may compare an input voltage transmitted through a single transmission line with a reference voltage.
FIG. 1 is a diagram for explaining a conventional method for generating an on-chip reference voltage Vref. Referring to FIG. 1, a DQ line 130 may be a single ended signal line connected between a transmitter 110 and a receiver 120. The reference voltage Vref may be generated by resistors R1 and R2 connected between a power supply voltage source VDDQ and a ground voltage source VSSQ. The receiver 120 may compare data transmitted through the DQ line 130 to the reference voltage Vref to determine whether the data is at a logic high level or at a logic low level. The reference voltage Vref may be shared by a plurality of DQ lines arranged in parallel.
In this case, noise generated in the power supply voltage source VDDQ of the receiver 120 may be applied to the DQ line 130 and the reference voltage Vref in a common mode, and/or the noise may be removed in the receiver 120. However, noise generated in the power supply voltage source VDDQ and the ground voltage VSSQ of the transmitter 110 may be applied only to the DQ line 130 and/or noise generated in the ground voltage VSSQ of the receiver 120 may be applied only to the reference voltage Vref.
FIG. 2 is a diagram for explaining a conventional method of generating a reference voltage Vref for improving the conventional method illustrated in FIG. 1. Referring to FIG. 2, a transistor 211 may be turned on in response to a reference voltage generating signal H provided by a transmitter 210. First and second resistors R1 and R2 serially connected to a power supply voltage source VDDQ of a receiver 220 may be connected to a ground voltage source VSSQ through the transistor 211 of the transmitter 210. The reference voltage Vref may be generated according to voltage distribution by the first and second resistors R1 and R2. The reference voltage Vref may be shared by a plurality of DQ lines 230 arranged in parallel. Ground voltage common noise of the transmitter 210 may be applied to both the DQ lines 230 and the reference voltage Vref and/or ground voltage common noise of the receiver 220 may not be applied to both the DQ lines 230 and the reference voltage Vref. Accordingly, the method illustrated in FIG. 2 may have higher noise removal capability than the method illustrated in FIG. 1.
However, if the number of the DQ lines 230 arranged in parallel is increased, the reference voltage Vref has to be supplied to more distant DQ lines. The power supply voltage source VDDQ provided to the DQ lines 230 may have different noise values due to voltage drop according to resistances of power supply lines in a chip. Accordingly, there may be generated a difference between common noise generated in the power supply voltage source VDDQ of the DQ lines 230 and common noise applied to the reference voltage Vref.
Input capacitance of a reference voltage line may be larger than input capacitance of the DQ lines 230 because the plurality of DQ lines 230 may be coupled to the reference voltage Vref. Accordingly, RF noise applied to a channel may have different values if applied to the DQ lines 230 and the reference voltage Vref. The phase of noise generated in the transmitter 210 may be varied in the receiver 220 and the noise may act as peaking because there may be a difference between the length of the channel between the reference voltage Vref and a distant DQ line and the length of other channels.